Conformal 3d non-planar multi-layer circuitry

ABSTRACT

A method for making conformal non-planar multi-layer circuitry is described. The method can include providing a substrate having a non-planar surface and depositing a first conformal dielectric layer on the substrate, the first conformal dielectric layer conforming to the non-planar surface of the substrate and having a non-planar surface. The method can also include applying a first conformal circuitry layer on the first conformal dielectric layer. The method can include depositing a second conformal dielectric layer on the first conformal circuitry layer, the second conformal dielectric layer conforming to a non-planar surface of the first conformal circuitry layer, and applying a second conformal circuitry layer on the second conformal dielectric layer. Successive layers can be sequentially deposited.

Embodiments relate generally to electronics circuitry and, more particularly, to conformal 3D non-planar multi-layer circuitry.

Conventional approaches to printed circuit boards (or printed wiring boards) often use rigid, planar substrates.

Weight or volume constraints may limit the use of rigid printed circuit boards in certain applications. Also, mechanical envelope requirements may limit use of planar circuit boards. A need may exist for multi-layer circuitry that conforms to a non-planar 3D surface.

Embodiments were conceived in light of the above problems and limitations of some conventional circuitry types, among other things.

One embodiment includes a method for making conformal non-planar multi-layer circuitry. The method can include providing a substrate having a non-planar surface and depositing a first conformal dielectric layer on the substrate, the first conformal dielectric conforming to the non-planar surface of the substrate and having a non-planar surface. The method can also include applying a first conformal circuitry layer on the first conformal dielectric layer, such that the first conformal circuitry layer conforms to the non-planar surface of the first conformal dielectric, the first conformal circuitry layer having a non-planar surface. The method can further include depositing a second conformal dielectric layer on the first conformal circuitry layer, the second conformal dielectric layer conforming to the non-planar surface of the first conformal circuitry layer, and applying a second conformal circuitry layer on the second conformal dielectric layer. Successive layers can be sequentially deposited to build up a multilayer circuit structure using microvias between circuit layers for electrical connections.

One embodiment includes a method for making non-planar, multi-layer circuitry. The method can include providing a substrate having a non-planar surface and depositing a first conformal dielectric layer on the non-planar surface of the substrate via vapor deposition, the first conformal dielectric conforming to the non-planar surface of the substrate and having a non-planar surface. The method can also include applying a first conformal circuitry layer on the first conformal dielectric layer, such that the first conformal circuitry layer conforms to the non-planar surface of the first conformal dielectric, the first conformal circuitry layer having a non-planar surface and including a first seed layer and a first conductor layer. The method can further include depositing a second conformal dielectric layer on the first conformal circuitry layer, the second conformal dielectric layer conforming to the non-planar surface of the first conformal circuitry layer. The method can also include applying a second conformal circuitry layer on the second conformal dielectric layer, the second conformal circuitry layer including a second seed layer and a second conductor layer.

Applying the first conformal circuitry layer can include applying the first seed layer on the first conformal dielectric layer and applying the first conductor layer on the first seed layer. Applying the first conformal circuitry layer can also include depositing resist material on the first conductor layer and etching the resist material to reveal portions of the first conductor layer and the first seed layer to be etched away. Applying the first conformal circuitry layer can further include etching the first conductor layer, etching the first seed layer, removing remaining resist material, and then filling and leveling any cavities or voids created during the etching of the first conductor layer and the first seed layer (e.g., using an epoxy solder mask material). Each of the first and second seed layers can include an alloy having chrome and copper. Each of the first and second conductor layers can include copper.

In one embodiment, applying the second conformal circuitry layer can include drilling vias in the second conformal dielectric layer. The drilling can be performed using a laser.

The non-planar surface of the first conformal dielectric layer can be etched to roughen the non-planar surface of the first conformal dielectric layer. The etching can be performed using oxygen plasma etching. Etching the resist can include laser imaging or ablation.

One embodiment includes a conformal non-planar multi-layer circuit comprising a substrate having a first non-planar surface and a first conformal dielectric layer on the substrate, the first conformal dielectric conforming to the first non-planar surface of the substrate and having a second non-planar surface. The circuit can also include a first conformal circuitry layer applied on the first conformal dielectric layer, the first conformal circuitry layer conforming to the second non-planar surface of the first conformal dielectric, the first conformal circuitry layer having a third non-planar surface. The circuit can further include a second conformal dielectric layer deposited on the first conformal circuitry layer, the second conformal dielectric layer conforming to the third non-planar surface of the first conformal circuitry layer and having a fourth non-planar surface. The circuit can also include a second conformal circuitry layer applied on the second conformal dielectric layer, the second conformal circuitry layer conforming to the fourth non-planar surface of the second conformal dielectric, the second conformal circuitry layer having a fifth non-planar surface. Successive layers can then be sequentially deposited to build up a multilayer circuit structure using microvias between circuit layers for electrical connections.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a chart showing an exemplary method for making non-planar multi-layer circuitry in accordance with at least one embodiment.

FIG. 2 is a chart showing an exemplary method for making non-planar multi-layer circuitry in accordance with at least one embodiment.

FIGS. 3-7 are diagrams showing cross sections of various stages of an exemplary non-planar multi-layer circuit being made in accordance with at least one embodiment.

DETAILED DESCRIPTION

In general, deposition processes and lithographic laser patterning are used to sequentially build up layers of copper circuitry on non-planar surfaces, including angled and curved surfaces. The non-planar, multi-layer circuitry can be formed on a variety of substrate materials including metallic, ceramic, and/or plastic substrates.

The non-planar, multi-layer circuitry can be used to build, for example, conformal antennas, conformal circuitry over enclosure structures, power circuitry built directly on heat sinking frames, and functional circuitry residing in a non-planar object, such as a helmet.

FIG. 1 shows an exemplary method 100 for making non-planar multi-layer circuitry. The method 100 starts at 102 and continues to 104.

At 104, a substrate is provided. The substrate can be a substrate having a non-planar 3D surface (e.g., an anodized aluminum component). Processing continues to 106.

At 106, a circuit layer is applied to the substrate. An example of the preparation of the substrate and application of a circuit layer is described in greater detail below in conjunction with FIG. 2. Processing continues to 108.

At 108, micro vias are drilled. Micro vias can be used to connect one circuit layer to another circuit layer. The drilling of micro vias is optional and depends on a contemplated circuit design. The micro vias can be drilled with a laser. Processing continues to 110.

At 110, it is determined whether additional circuit layers are needed. If so, processing continues to 106. If not, processing continues to 112, where the process ends.

FIG. 2 is a chart showing an exemplary method for making non-planar multi-layer circuitry in accordance with at least one embodiment. The method begins at 202 and continues to 204.

At 204, a dielectric layer is applied. When the first circuit layer is being formed, the dielectric layer can be applied to a substrate. For subsequent circuit layers, the dielectric is deposited on the preceding circuit layer. The dielectric can be applied using a vapor deposition process. For example, the dielectric layer can be formed from Parylene HT at a thickness of about 2 mils. Parylene HT is available from Specialty Coating Systems of Indianapolis, Ind. Other suitable dielectric materials can be used. The process continues to 206.

At 206, the surface of the dielectric layer is etched. The etching is done to roughen the surface of the dielectric for better adhesion with subsequent layers. The etching can be done using oxygen plasma. Other etching techniques can be used. The process continues to 208.

At 208, a seed layer of metal is applied. For example, the seed layer can include a chrome/copper (Cr/Cu) alloy applied using sputtering to a thickness of about 1 micron. The process continues to 210.

At 210 the conductor layer is applied. For example, the conductor layer can include copper applied using sputtering and/or electroplating to a thickness of about half a mil (12.7 microns). The process continues to 212.

At 212, a layer of resist material is deposited. The resist material can include any suitable resist material that can resist the etching solutions used to etch the conductor layer and the seed layer. The process continues to 214.

At 214, the resist material is imaged or etched with the circuit pattern. The patterning of the resist material can be performed using a laser. For example, a laser can be used to pattern channels in the resist to facilitate conductor layer etching for fabrication of circuit lines and spaces down to about 3 mils wide. The process continues to 216.

At 216, the conductor and seed layers are etched using etching solutions appropriate to etch the material of each layer. The process continues to 218.

At 218, the resist material is removed (or stripped). The process continues to 220.

At 220, any cavities or voids created during the etching process are filled. For example, the spaces between lines can be filled with an epoxy solder mask material. The process continues to 222 where the process ends. It will be appreciated that 202-222 can be repeated for each layer of a multi-layer circuit. In a multi-layer circuit, the dielectric material applied on top of a preceding layer can be drilled to form micro vias that permit the conductor of a next layer to connect with the conductor of the preceding layer. The drilling could occur, for example, between 206 and 208.

FIGS. 3-6 are diagrams showing cross sections of various stages of an exemplary non-planar multi-layer circuit being made in accordance with at least one embodiment.

FIGS. 3 and 7 each show an exemplary section of a partially built circuit 300 or 700 having a substrate layer 302 or 702, a first circuit layer 304 or 704 and a dielectric layer 306 or 706. The substrate has a non-planar feature 308 or 708 resulting in a non-planar top surface. Depending on the type of substrate and a contemplated design, a dielectric layer can be applied to the top surface of the substrate. The dielectric layer can conform to the substrate and have a top surface with a non-planar feature that corresponds to the non-planar feature 308 of the substrate.

The first circuit layer 304 can be applied directly to the substrate 302 or to a dielectric layer (e.g., dielectric layer 703 in FIG. 7) applied to the substrate. The first circuit layer 304 conforms to the underlying layer and takes on a non-planar shape and has a top surface that is non-planar. The next dielectric layer 306 is applied on top of the first circuit layer 304 and conforms to the non-planar top surface of the first circuit layer 304 and has a non-planar top surface.

Prior to applying a next circuit layer, a micro via (402 in FIG. 4) can be drilled through the dielectric layer 306. The micro via can be drilled using a laser or other suitable technique.

As shown in FIG. 5, when a second circuit layer 502 is applied to the circuitry 500, the second circuit layer 502 connects with the first circuit layer 304 where the micro via 402 was drilled. Also, the second circuit layer 502 conforms to the non-planar top surface of the dielectric layer 306 and has a top surface that is non-planar. As described above, a circuit layer can include a seed layer and a conductor layer.

Any voids created while forming the circuit layers (e.g., the void where micro via 402 was drilled) can be filled and leveled (602 of FIG. 6) using, for example, an epoxy solder mask material. The resulting circuitry 600 is multi-layer (e.g., 304 and 502), conformal and non-planar.

It is, therefore, apparent that there is provided, in accordance with the various embodiments disclosed herein, conformal 3D non-planar multi-layer circuits and methods for making the same.

While the invention has been described in conjunction with a number of embodiments, it is evident that many alternatives, modifications and variations would be or are apparent to those of ordinary skill in the applicable arts. Accordingly, Applicants intend to embrace all such alternatives, modifications, equivalents and variations that are within the spirit and scope of the invention. 

1-20. (canceled)
 21. A method of forming a multi-layer circuit, comprising: providing a substrate having a first non-planar surface; forming a conformal circuitry layer over the substrate, the conformal circuitry layer conforming to the first non-planar surface of the substrate, and the conformal circuitry layer having a second non-planar surface; and forming a copper circuitry layer over the conformal circuitry layer, the copper circuitry layer conforming to the second non-planar surface of the conformal circuitry layer, and the copper circuitry layer having a third non-planar surface.
 22. The method of claim 21, further comprising: depositing a conformal dielectric layer over the copper circuitry layer, the conformal dielectric layer conforming to the third non-planar surface of the copper circuitry layer, and the conformal dielectric layer having a fourth non-planar surface.
 23. The method of claim 22, wherein the depositing the conformal dielectric layer includes performing a vapor deposition process until the conformal dielectric layer has a thickness of about 2 mils.
 24. The method of claim 21, further comprising: depositing a conformal dielectric layer over the substrate, the conformal dielectric layer conforming to the first non-planar surface of the substrate and the conformal dielectric layer having a fourth non-planar surface.
 25. The method of claim 24, further comprising: drilling at least one micro via into the conformal dielectric layer, the at least one micro via exposing the conformal circuitry layer, wherein the copper circuitry layer contacts the conformal circuitry layer through the at least one micro via.
 26. The method of claim 21, wherein the forming of the conformal circuitry layer includes sputtering or electroplating a chromium-copper alloy layer over the substrate.
 27. The method of claim 26, wherein the chromium-copper alloy layer has a thickness of about 1 micron.
 28. The method of claim 21, wherein the forming of the copper circuitry layer includes sputtering or electroplating a chromium-copper alloy layer over the conformal circuitry layer.
 29. The method of claim 21, wherein at least one of the conformal circuitry layer and the copper circuitry layer has a thickness of about 12.7 microns. 